In the field of electronic devices, and in particular the field of synchronous digital systems, it is known for a clock signal to be used to define a time reference for a transition of states within functional elements of such synchronous digital systems. As such it is known to implement a clock distribution network, sometimes referred to as a clock tree when comprising a general tree-like form, which typically receives one or more clock signals as inputs, and distributes the received clock signal(s) to functional elements within the synchronous digital system.
Such clock distribution networks often comprise a significant ‘fan-out’, and operate at extremely high speeds. Furthermore, the clock waveforms are required to be particularly clean and sharp, since they provide a temporal reference to the rest of the synchronous digital system. As a result, clock distribution networks are particularly affected by technology scaling, in that long interconnect lines become significantly more resistive as line dimensions are decreased. Consequently, clock distribution networks have a significant impact on the maximum performance of an entire synchronous digital system.
Furthermore, a clock distribution network often takes a significant fraction of the power consumed by an integrated circuit (IC) device in which it is implemented. It is known to implement clock gating as a basic power saving technique. The technique of clock gating typically comprises ‘gating’ portions of an IC's clock distribution network relating to parts of the IC that are not required to be clocked under certain operating conditions. In this manner, when such a part of the IC is not required to be clocked, the part of the clock distribution network relating to that part of the IC may be ‘gated off’, in order to disable the clock signal to that part of the IC, thereby stopping further data/signal bit transitions and saving power. More effective clock gating, such that may provide greater power savings, may be achieved by providing the clock gating earlier in the clock distribution network.
A problem with the concept of clock gating is that setup timing violations result in an inherent latency between a decision to ‘wake-up’ a part of an IC device for which a part of the clock distribution network has been ‘gated off’, and achieving the re-initialisation of that part of the clock distribution network and the waking up of the corresponding part of the IC device. Such latency has a detrimental impact on the achievable operating frequency of the circuit in which it is implemented. Such a detrimental impact on the achievable operating frequency of the circuit is especially significant for high speed circuit designs and systems. For example, a signal processing system that was shown to be able to operate at 1.2 Ghz without clock gating may be reduced to only being able to operate at around 1050 MHz when clock gating is implemented, due to setup timing violations of, say, approximately 120 ps using current circuit design techniques.